The present invention relates to a Single Event Upset (SEU) resistant circuit. More specifically, the present invention uses n-channel and p-channel transistors in a latch cell design to achieve a latch cell resistant to SEU.
Radiation can have detrimental effects on electronics, including immediate temporary information upset and increased power consumption as a circuit responds to a single event upset (SEU) event. Ionizing radiation occurs in the form of charged particles that possess enough energy to break atomic bonds and create electron/hole pairs in the absorbing material. Such particles may include protons, electrons, atomic ions, and photons with energies greater than the material band gaps. The primary ionizing radiation effects on microelectronics can be categorized as either total ionizing dose (TID) effects or transient effects. TID effects are a function of ionizing radiation accumulation over months or even years, which can lead to performance degradation and functional failure. Transient radiation effects are primarily the result of photo-currents generated as energetic particles pass through the circuit.
The SEU occurs when the charge collected as a result of the generated photo currents is of sufficient magnitude to alter the logic state of a susceptible node. An upset node may further cause the alteration of the contents of circuit memory elements or alter the operation of the circuit in such a way to cause an error in a logic function.
There are existing designs that mitigate SEU events. One such design is known as the DICE Memory Cell 10 shown in FIG. 1. An analysis of this circuit is illustrated in a state table shown in FIG. 2. The inputs for each of the y0 and y1 nodes of FIG. 1 are shown on the horizontal line above the chart. The inputs for each of the y2 and y3 nodes of FIG. 1 are shown in the vertical line to the left of the chart. The resulting state for each of the four nodes y0, y1, y2 and y3, are shown in each corresponding box in the chart. The stable states (normal operation state) are 0101 and 1010 because at these input states the DICE cell retains its input state at the output nodes. In normal operation, the circuit transitions between these two states.
An entry of X in the chart represents a conflict condition in that both transistors shown in a stack of FIG. 1 are conditioned to conduct. Thus, the upper transistor attempts to pull the node high, while the lower transistor attempts to pull the node low. This also causes the circuit to draw excessive current. Likewise, an entry of Z in the chart represents a high impedance condition in that both transistors in a stack are conditioned to be in a cut-off mode. Thus, the node floats, and retains its condition because of the node""s capacitance. When the NMOS devices are stronger than the PMOS devices, all the X states are changed to 0 since the NMOS transistor will win the conflict state although higher than normal current still exist during the conflict.
It is possible to predict the action of the circuit state given the next state table. By way of example of the operation of the DICE memory cell, the circuit is assumed to be in the stable state 0101 while an SEU event occurs that changes y2. Therefore the stable state is changed to 0111. The next state entry for 0111 is 000Z, (assuming that the NMOS devices are stronger) which means the circuit will be driven to 0001, but will consume higher than normal supply current in order to resolve the conflict. Not all variables change at the same instant. Suppose state variable y1 changes to a 0 first causing the circuit to enter state 0011, which has a next state entry of Z00Z. Only state variables y1 and y2 are driven, in this case to 0, but y1 already is 0. Therefore only y2 will change causing the circuit to assume 0001, which has a next state entry of Z101. Next state variable y1 will be excited to change forcing the circuit back to the original state 0101. In the process of this set of transitions, the circuit has entered three unstable states (0111, 0011, 0001) before returning to the stable state. In these three unstable states, there were a total of 4 conflicts (4 sets of NMOS and PMOS devices that are both turned on). In addition, three transition times were needed to return the circuit to its stable state. The DICE Cell 10 draws a large amount of current because the circuit has to go through many high-current transitions from an unstable to a stable state.
Another design aimed to mitigate the SEU is the Whitaker design shown in FIG. 3. In the U.S. Pat. No. 5,111,429, entitled, xe2x80x9cSingle Event Upset Hardening CMOS Memory Circuitxe2x80x9d by Whitaker, the inventor shows that the Whitaker cell 30 is a 4-state variable asynchronous circuit that has the capability of resisting the forces of an SEU. However, in this design, there are also many conflicts. A difference between the Whitaker cell 30 and the DICE Cell 10 is that the Whitaker cell 30 takes advantage of the knowledge that SEU induced current flows in known directions associated with PMOS and NMOS devices respectively. Therefore, two of the state variables are realized with only PMOS devices and the other two state variables are realized with only NMOS devices. The state variables implemented with PMOS (NMOS) devices cannot experience an SEU failure which causes a 1 to 0 (0 to 1) transition. In addition to increasing current during conflicts, the Whitaker cell 30 produces degraded signal levels due to the presence of PMOS pull-down devices (pass Vss through a PMOS transistor) and the presence of NMOS pull-up devices (pass Vdd through an NMOS transistor). These degraded signal levels mean that some transistors are never fully off and they have significant static leakage current. Therefore, there are two sources of increased current relative to classical CMOS designs. The first source is the conflicts in the design itself, and the second source is the state variables which are composed of only PMOS or only NMOS devices. There are two aspects of the prior art design that make it disadvantageous for ultra low power applications. First, the degraded logic levels inside the storage cell make it more difficult to lower the supply voltage. For example, if a PMOS transistor is used as a pull-down then the resulting logic level will be no lower than one transistor threshold above ground. If this signal is then used to drive a second PMOS transistor with its source at Vdd, then Vdd must be made somewhat greater than twice the transistor threshold so that the degraded 0 will be low enough to enable the second PMOS device. If there are no degraded signals then Vdd can be lowered to a level somewhat greater than one transistor threshold. Since dynamic power consumption is proportional to the square of the supply voltage this can provide a significant savings.
Second, operation at very low supply voltage requires that transistors have correspondingly low threshold voltages. As a consequence, the sub-threshold leakage of these transistors may be quite large, perhaps as much as 10% of the transistor""s saturation current. Any circuit that relies on relative transistor strength ratios, such as the prior art DICE 10 and Whitaker cells 30, will not function well under these conditions. Suppose that a circuit is designed so that conflicts between a pull-up transistor and a pull-down transistor always resolve to a zero xe2x80x9c0xe2x80x9d, and the pull-down transistor is made five times stronger to accomplish this goal. The sub-threshold leakage through this transistor, at 10% of its saturation current, will be equal to half of the saturation current of the weak pull-up, and the pull-up transistor will be unable to create a correct xe2x80x9c1xe2x80x9d level. Decreasing the strength of the pull-down transistor allows the pull-up transistor to create a higher xe2x80x9c1xe2x80x9d level but makes it more difficult for the pull-down to properly resolve conflict to a xe2x80x9c0xe2x80x9d state. At best, the prior art circuit will operate very slowly and at worst it will cease to function.
To overcomes these problems, Barry and Dooley in U.S. Pat. No. 5,157,625 by Barry and in U.S. Pat. No. 5,311,070 by Dooley tried to overcome the problems in the Whitaker and DICE cells related to conflict states and degraded signal levels. Furthermore, the Barry/Dooley cell succeeded in recovering from a single fault event with only one transition. The generalized design equations are:
y0=yxe2x80x22yxe2x80x23(1)+y2y3(0)
y1=y2xe2x80x2y3xe2x80x2(1)+y2y3(0)
y2=y0xe2x80x2y1xe2x80x2(1)+y0y1(0)
y3=y0xe2x80x2y1xe2x80x2(1)+y0y1(0)
The first term on the right hand side of the first equation, y2xe2x80x2y3xe2x80x2(1) indicates the conditions that will cause y0 to be driven to the 1 state. In this case y0 is driven to 1 when both y2 and y3 are low. The second term on the right hand side of the first equation, y2y3(0), indicates the conditions that will cause y0 to be driven to the 0 state. In this case y0 is driven to 0 when both y2 and y3 are high. It is impossible to drive y0 to the 1 and 0 states simultaneously, so node 0 is free of conflicts. However, if y2 and y3 are in opposite states then y0 is not driven and is left in a high impedance state, holding its previous logic level by virtue of the capacitance on this node.
The stable states in the Barry/Dooley design are 1100 and 0011. This design can transition only a distance one from a stable state upon an impact of an SEU. The letter Z denotes high impedance state for the given state variable. In this design, NMOS transistors pass only 0 and PMOS transistors pass only 1. To illustrate SEU tolerance, consider the design equations and the following. Let the circuit to be in state y0y1y2y3=1100. Assume an SEU causes y0 to be transitioned from 1 to 0. The circuit would transition to 0100 at which time both y2 and y3 go to the high impedance state and the circuit transitions to 01ZZ. The charge on y2 and y3 will hold these two nodes at the 0 state, hence the circuit remains stable until the SEU effect is removed. Once the SEU effect is removed, the charge on the nodes y2 and y3 will force y0 to the 1 state and force the circuit back to 1100; next state variable y2 and y3 are actively driven to 0 and this state once again is stable.
Consider the example where an SEU causes y2 to transition from 0 to 1. The circuit transitions to 1110 at which time both y0 and y1 go to the high impedance state and the circuit transitions to ZZ10. The charge on the nodes for y0 and y1 will keep y3 active at the 0 state, hence the circuit remains stable until the SEU effect is removed. Once the SEU effect is removed, the charge on the nodes for y0 and y1 will force y2 to the 0 state and force the circuit back to 1100; next state variables y0 and y1 are forced to 1.
The Dooley/Barry design has more transistors, and hence a greater area than is necessary.
Therefore, what is needed is an invention that has no conflict states, is relatively insensitive to the relative sizes of the transistors in the cell and uses a fewer number of transistors.
The present invention in its preferred embodiment represents the circuit design configuration called Single Event Resistant Topology (SERT) to achieve a low-power SEU tolerant circuit using fewer transistors than the prior art. Within the SERT configuration, the circuit operation is insensitive to the relative sizes of the transistors in the cell. There are two essentially equivalent embodiments of the SERT cell. The first embodiment or SERT-1 comprises 8 PMOS transistors cross-coupled to four NMOS load transistors. The second embodiment or SERT-2 comprises 8 NMOS transistors cross-coupled to four PMOS load transistors.
The nature, principle and utility of the present invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings.